The present invention relates to the etching of an indium tin oxide (ITO) layer in a plasma reactor. More particularly, the present invention relates to an improved method for dry etching portions of an ITO layer in a low pressure, high density plasma reactor, such as a transformer coupled plasma (TCP.TM.) reactor.
The popularity of indium tin oxide (ITO), which comprises tin oxide doped with indium, in the manufacture of optical devices and integrated circuits (ICs) may be attributed to its high electric conductivity and good optical transmittance. Early on, ITO films were commonly employed in transparent electric heaters for aircraft windows and antistatic coatings on instrument panels. Its use has expanded since and now includes antireflection coatings, heat reflecting mirrors, transparent electromagnetic shield coatings, transparent electrodes, and optoelectronic and photovoltaic devices such as heterojunction solar cells, transparent electrodes for various electrical devices such as photodetectors, and optical waveguides. For more information on the various applications of ITO, see for example, S .A. Knickerbocker and A. K. Kulkarni "Calculation Of The Figure Of Merit For Indium Tin Oxide Films Based On Basic Theory" J. Vac. Sci. Technology., Vol. 13, No. 3, pp.1048-1052 (1995).
One of the more notable areas of applications has been in the manufacture of flat panel displays, e.g., for wall mount televisions or laptop computers, thin film transistor-liquid crystal displays such as high resolution monitors, viewfinders, fine-pixel projectors, and the like. For discussion purposes, a cross sectional diagram of a representative panel portion 100 containing a layer of ITO is shown in FIG. 1A. Panel portion 100, which represents a portion of a flat panel display may include a glass substrate 106. Glass substrate 106 may represent, for example, a 320.times.340 mm.sup.2 Dow Corning 7059.RTM. or 1739.RTM. glass substrate, available from Dow Corning Corp. of Michigan and is well known to one skilled in the art. The glass substrate may include SiO.sub.2, low temperature glass or high temperature quartz. Above glass substrate 106, there is disposed a layer stack, a portion of which is shown in FIG. 1A as a layer of indium tin oxide (ITO) layer 104. Above ITO layer 104, there is shown a photoresist layer 102.
It should be noted that the devices of the figures shown herein are depicted in a simplified format for illustration purposes only. There may be present other additional layers above, below, or in between the layers shown. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers. The layers of the devices shown and discussed herein are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-etched chemical vapor deposition (PECVD), and a physical vapor deposition (PVD), such as sputtering.
During a typical ITO etching process, the photoresist layer is first patterned using an appropriate photoresist processing technique. By way of example, one such photoresist processing technique involves the patterning of photoresist layer 102 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of ITO layer 104 that are unprotected by the mask are then etched away.
During etching, portions of photoresist layer 102, ITO layer 104, and portions of substrate 106 (by way of the etched through regions of ITO layer 104) may all be exposed to the etchant plasma that is used to etch the ITO layer 104. Unless a high selectivity between ITO and glass and/or photoresist is achieved by the ITO etch process, undue portions of the protective photoresist features and/or the underlying glass substrate may be inadvertently etched away, thereby adversely impacting the etch resolution of the ITO layer. Since the etch resolution of the ITO layer relates directly to the "quality" and/or operation of the resulting display device, a high selectivity etch process is thus desirable.
A high ITO to silicon nitride (SiN.sub.x) selectivity is also desired as well. For discussion purposes, FIG. 1B shows a thin film array device 200, which may function as, for example, a light switch. In such a device, a portion of the ITO layer may be employed as a contact to the pixel electrode. Referring now to FIG. 1B, there is shown in device 200 a first electrode layer 204, which may include, for example, chromium and may be disposed on a glass substrate 202. Above first electrode layer 204, there may be disposed a gate dielectric layer 216, which may comprise, for example, silicon nitride and/or silicon dioxide.
Above gate dielectric layer 216, there is disposed an active layer 206, which may comprise, for example, amorphous silicon. An ohmic contact layer 208 may be disposed above gate dielectric layer 216. Ohmic contact layer 208 may include, for example, p-doped (n.sup.+) amorphous silicon. Ohmic contact layer 208, in turn, may be disposed under a second electrode layer 210. A passivation layer 212, which may include silicon nitride (SiN.sub.x), may be disposed above second electrode layer 210.
A contact hole 214 through passivation layer 212 permits a pixel electrode 218 to make electrical contact with underlying second electrode layer 210. Pixel electrode 218 may include ITO, and may be formed by a blanket deposition of the ITO material, followed by an etch back step to create pixel electrode 218.
During the etching of the blanket-deposited ITO layer to create pixel electrode 218, portions of the ITO are removed. Since portions of the ITO layer and passivation layer 212 may be exposed to the etchant plasma during the pixel electrode contact etch, however, some removal of passivation layer 212 may result. Because of the possibility of unwanted silicon nitride removal, a high ITO to silicon nitride selectivity is generally desirable.
In conventional ITO etching processes, dry etching is generally not favored because ITO etch products do not volatilize easily. The dry etch, when employed, is typically conducted in a high pressure (&gt;100 milliTorr), low flux density plasma reactors, e.g., those employing parallel plates, where an etchant gas is introduced for etching. Further, prior art high pressure, low density, dry etching processes involve several known disadvantages. Prior art high pressure, low density etching processes using organic gases such as methane, acetone, ethanol, and methanol, for example, suffer from polymer formation due to a high concentration of hydrocarbon radicals within the discharge. During prior art ITO etching processes, these processes form volatile organometallic compounds, which adhere to the reactor interior and tend to be difficult to remove during chamber cleaning. In fact, their removal is generally an arduous and time consuming process, which lowers the throughput of the etch reactor.
On the other hand, etching processes that use halogens, such as chlorine, iodine and bromine, under the high pressure, low flux conditions of the prior art tend to yield very low etching rates and form solid etch by-products that are also difficult to remove. Etchant gases such as hydrogen bromide and hydrogen iodide may have been employed, but the high pressure, low density conditions under which they were employed in the prior art necessitate an additional step of pre-heating the substrate. Pre-heating the substrate, while making the ITO material more volatile and easier to etch, introduces an additional step into the etching process, which makes the prior art dry etching techniques less economically attractive. It is further discovered that preheating may damage or reticulate the protective photoresist features.
Some of these disadvantages have prompted the prior art ITO processes to generally favor a wet etch approach. As is known, however, the wet etch approach also suffers from several drawbacks. For example, the wet etch rates are low and may be highly dependent on the ITO sheet resistance. Additionally, the conditions associated with wet etching are often hazardous, with the disposal of the etching solutions posing a significant safety hazard.
Still further, uniform etching of the ITO layer by wet etching is often difficult to achieve. Also, the etch selectivity to the overlying photoresist and/or the layers surrounding the ITO layer, such as silicon nitride, may be poor with the wet etch technique. In the view of above, what is desired is an improved method and apparatus for efficiently etching the ITO layer in a plasma processing chamber.